Problem 1: Solve H&P 7.7

Problem 2: Solve H&P 7.9

Problem 3: Solve H&P 7.29

Problem 4: Solve H&P 7.35

Homework #4 (Assigned 2/29/00), Due 3/7/00 -- at the beginning of lecture, 3:55pm)

Problem 1: Solve H&P 6.4

Problem 2: Solve H&P 6.10

Problem 3: Solve H&P 6.15

Problem 4: Solve H&P 6.26

Problem 5: Solve H&P 6.30

Homework #3 (Assigned 2/4/00, Due 2/11/00 -- at end of TA office hours, 3pm)

Problem 1: Solve H&P 3.13

Problem 2: Solve H&P 5.1

Problem 3: Solve H&P 5.10

Problem 4: Solve H&P 5.12

Problem 5: Solve H&P 5.13

Problem 6:

For this problem, use the gcc data from Figure 4.54 on page 311. Assume there are three machines:

·        M1: The multicycle datapath of Chapter 5 with 450MHz clock

·        M2: A machine like the multicycle datapath of chapter 5, except that register updates are done in the same clock as a memory read or ALU operation. Thus, in Figure 5.42 on page 396, states 6 and 7 and states 3 and 4 are combined. This machine has a 250Mhz clock, since the register update increases the length of the critical path

·        M3: A machine like M2, except that effective address calculations are done in the same clock cycle as a memory access. Thus states 2,3 and 4 can be combined, as can 2 and 5, as well as 6 and 7. This machine has a 100Mhz clock because of the long cycle created by combining address calculation and memory access.

Find out which machine is fastest. Are the instructions mixes that would make another machine faster, and if so, what are they ?

Problem 7:

In estimating the performance of the single-cycle implementation, we assumed that only the major functional units had any delay (i.e., the delay of the multiplexors, control unit, PC access, sign extension unit, and wires was considered to be negligible). Assume that we change the delays specified on page 373 such that we use different type of adder for simple addition:

·        ALU: 4ns

·        adder for PC+4: X ns

·        adder for branch address computation: Yns

 a)      What would the cycle time be if X=2 and Y=5 ?

 b)      What would the cycle time be if X=5 and Y=1 ?

 Problem 8:

 Same as problem H&P 5.15 but we wish to add the instruction ori (or immediate). See the back of the cover page of the book for a description of this instruction in the table MIPS Assembly Language.

Homework #2, Assigned 1/25/00, Due 2/3/00 (at the beginning of class)

 Problem 1:  Solve H&P 3.1

Problem 2:  Solve H&P 3.10

Problem 3:  Solve H&P 3.11

Problem 4:  Solve H&P 3.14

 Problem 5:

Suppose we have made the following measurements of average CPI for instructions:

Compute the effective CPI for MIPS. Average the instruction frequencies for gcc and spice in figure 3.38 on page 189 from the textbook to obtain the instruction mix.

Problem 6:

Several researchers have suggested that adding a register memory addressing mode to a load/store machine might be useful. The idea is to replace sequences of

            lw    $8, addr($3)

            add  $2,$2,$8

by

            addm $2,addr($3)

Assume the new instruction will cause the clock cycle to increase by 10%. Use the instruction frequencies for the gcc benchmark from figure 3.38 on page 189, and assume the two-thirds of the moves are loads and the rest are stores. Assume the new instruction affects only the clock speed and not the CPI.

a) What percentage of the loads must be eliminated for the machine with the new instruction to have at least the same performance?

b) Show a situation in a multiple instruction sequence where a load of $8 followed immediately by a use of $8 (with some type of opcode) could not be replaced by a single instruction of the form proposed, assuming that the same opcode exists.

Problem 7:

Same as exercise (3.19) in the textbook, except that the three assignments written in C code are replace by the single assignment:

            a = (x * y) - ( b * c); 

Where a, b, c, x, and y are variable in memory.

Problem 8:

Write a procedure, faverg, in MIPS assembly language. This procedure should take a single argument that is a pointer to a null-terminated array of integers in register $a0. The faverg procedure should compute the arithmetic mean of the integers in the array and return the value in register $v0.

Homework #1, Assigned: January 14, 2000, Due: January 24 (at beginning of Discussion section)

Solve the following problems, and turn in your solutions with sufficient information to show how you arrived at a solution. Please make sure your solutions are clearly and neatly presented. Indecipherable homeworks will be graded as incorrect.

Chapter I: Problems 1.50 and 1.54

Chapter II: Problems: 2.1, 2.2, 2.3, 2.4, 2.18, 2.19, 2.20, 2.25, and 2.33

For more information, email to Professor Andrew Chien

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