MORPH: Configurable Computing for Petaflops

(an NSF 100 Tera-ops Point Design)

Andrew A. Chien and Rajesh K. Gupta

Achieving 100 TeraOps performance within a ten-year horizon will require massively-parallel architectures that exploit both commodity software and hardware technology for cost efficiency. Increasing clock rates and system diameter in clock periods will make efficient management of communication and coordination increasingly critical. Configurable logic presents a unique opportunity to customize bindings, mechanisms, and policies which comprise the interaction of processing, memory, I/O and communication resources. This programming flexibility, or CUSTOMIZABILITY, can provide the key to achieving robust high performance.

The MultiprocessOr with Reconfigurable Parallel Hardware (MORPH) uses reconfigurable logic blocks integrated with the system core to control policies, interactions, and interconnections. This integrated configurability can improve the performance of local memory hierarchy, increase the efficiency of interprocessor coordination, or better utilize the network bisection of the machine. MORPH provides a framework for exploring such integrated application-specific customizability. Rather than complicate the situation, MORPH's configurability supports component software and interoperabilty frameworks, allowing direct support for application-specified patterns, objects, and structures.

These pages report the motivation, design, and initial evaluation of reconfigurable architectures (MORPH class machines). By using traditional scientific applications (partial differential equation solvers for computational fluid dynamics) and emerging scientific applications (graphics and visualization codes), we evaluate the utility of configurability in efficient memory hierarchy management. Our results show that incorporating flexibility can significantly increase MEMORY EFFICIENCY, utilizing the fast cache memory more efficiently to reduce effective memory latency and memory bandwidth requirements. Across applications, we find that the required optimizations are different, supporting the approach of configurability. Estimates of hardware complexity using hardware synthesis tools are provided to quantify the cost/performance trade-offs.

Presentations on MORPH

• Petaflops II at Frontiers '96, October 1996
• Petaflops Architecture Workshop, April 1996

Additional Information (papers and reports)

• MORPH: A System Architecture for Robust High Performance using Customization (Frontiers '96)
• Architectural Adaptation for Application-specific Locality Optimization (ICCD '97)
• Morph Point Design Study Project Report (in progress)
• Morph Study Performance Data (in progress)
• Morph Study Hardware Complexity Data (in progress)

Funding information

The MORPH project is supported by the National Science Foundation

Last updated October 1996