CS 491 Hardware and Software Architecture for Parallel Servers

(nominally Architecture and Design of Large Scale Parallel Systems)

Professor Andrew A. Chien 2215 DCL, x3-6844, achien@cs.uiuc.edu.

Credit: 1/4 unit (NOTE: Inadvertently listed for 1/2 unit, please be sure to register for 1/4 unit)

Prerequisites: Consent of Instructor

Meeting Time: Tuesdays, 11am - 12:30, 2262 DCL.

Web site: http://www-csag.cs.uiuc.edu/individual/achien/cs491-s96/cs491.html

This seminar will focus on the following topics:

Clustering systems for high performance (Web servers, compute servers, etc.)
High performance communication software and hardware (scalable TCP, MPI, ATM, etc.)
Interactive multimedia software and hardware (real-time and quality of service)
High speed network protocol design and processing

There is a reading list. As usual, the seminar will focus on discussing real systems, implementations, and the key challenging research issues.

Organization and Work:

Students will be expected to take an active role in the seminar. This will include weekly attendance, reading the assigned papers in advance, active participation in discussions, and giving two mini-presentations over the course of the semester. For each week there will be a protagonist and an antagonist. The roles are defined as follows:

Protagonist presents the perspective described by the paper, and acts acts as an advocate for its ideas and results on the basis of substantive technical arguments. (20 mins)
Antagonist presents a counterpoint to the paper, asking some penetrating questions, and advocating an alternative point of view on the basis of substantive technical arguments (10 mins).

Of course all of the seminar attendees will be expected to participate actively in the ensuing melee.

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achien@cs.uiuc.edu